Jobbeschreibung
- Work with systems team to understand the top level requirements of the digital functions and develop detailed specifications- Implement the function in Verilog RTL to specification - Partition the function between HW and FW for most efficient implementation- Develop RTL and FW to implement the function- Perform unit level testing on the RTL functionOther responsibilities could include:- RTL synthesis- Equivalence checking Static Timing Analysis- Develop FW to support DV and ATE environments- Support the DV team by writing self-checking tests as required
Anfrage
Experience in digital design including RTL design experienceKnowledge of best practices with respect to implementation of digital logicUnderstanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation, equivalence checkingUnderstanding of Design Verification (DV) and the ability to write self-checking test suitesAbility to write assembly level code and higher level codeAbility to analyze a design and partition between HW implementation and SW controlExperience in hands-on lab evaluationUnderstanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generationTeam player with excellent written and verbal communication skills who has the desire to seek diverse challenges with international teamsAbility to work well with international teams, take ownership and motivate self and othersProficiency in English language is required
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Adresse
Germany
