Jobbeschreibung
You will closely collaborate and engage with members of cross-functional disciplines including design teams, digital verification, system engineers and architects, and DfT teams to define and execute the verification strategy and test plan to cover a specified feature or IP. Your tasks would include:- Develop analog behavioral models with different abstraction levels based on required verification targets- Development of test plans covering the specified feature set and related checks and assertions- Design verification from interactive test case debugging to automated regressionAnalysing verification results and debugging the design- Planning and reviewing the verification results with cross-functional stakeholders- Collaborating with design and DV teams targeting optimum verification coverage- Construction of verification and modeling environment using leading edge methods- Verification automation
Anfrage
Experience in analog and mixed-signal verification and circuit modelingUnderstanding of analog schematics and digital RTL to support and analyse verification resultsUnderstanding of behavioral modeling and model validation techniquesKnowledge of Verilog-AMS, Verilog, and System-VerilogHands-on experience with Assertion Based VerificationKnowledge of verification automation concepts and scripting languages: TCL, Python/Perl is an advantageKnowledge of UVM (Universal Verification Methodology) is a plusProactive team player with excellent communication skills able to collaborate with diverse cross-functional teamsBackground in power management is a plusFluency in English is required
Heim
Profil 123work
Wieder aufnehmen
Motivationsschreiben
Adresse
Germany
