Jobbeschreibung
Construction of verification environment by using Verilog, System Verilog or UVM Designing test plan for verification Coding test scenarios, assertion and debugging for Digital Design.
Anfrage
Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)Hands-on experience with constrained random verification environmentsHands-on experience with Assertion Based VerificationBasic design background in support of verification results analysisKnowledge of Object Oriented Programming (OOP)Familiarity with system design using C (C++) or Verilog is a plusATE functional test pattern generation for logic testers is a plusProficiency in English language is required
Heim
Profil 123work
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Adresse
Germany
