Jobbeschreibung
- Detailed transistor level layout of analog circuit blocks - Block level and top-level layout through full verification flow including DRC, LVS, PERC, EM/IR and DFM checking - Co-work with designers on block level and top-level floor-planning including area and effort estimation- Execute peer reviews for critical and major layout blocks- Layout according to DFM rules - Top-level layout integration and verification - Schedule management and tracking
Anfrage
Several years of experience in custom analog layout with extensive knowledge on planar and preferably non-planar CMOS technologiesCapability to lead other layout engineers for top-level integration.Knowledgeable on layout techniques for device matching, power routing and minimising parasiticsYou understand issues of RC delay, electromigration, and cross capacitanceExperience with Power Management circuit layout would be an assetMust recognise failure prone circuit and layout structures, dedicatedly work with circuit designer for best approach to problemsHigh level proficiency in interpretation of Calibre DRC, ERC, LVS, etc.Knowledge of Mentor Graphics and Cadence layout toolsUnderstanding of IO/ESD and LUPScripting skills in PERL or SKILL are considered a plus, but not requiredFluency in English is requiredExcellent interpersonal skills and able to work with multi-functional teams
Heim
Profil 123work
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Adresse
Germany
